1. Field of the Invention
The present invention relates to a digital signal processor (DSP) for controlling an analog circuit device. The present invention can be advantageously used to control phase shifters of antennas of a phased array radar.
2. Description of Related Art
A structure of a typical phased array radar is explained in the following. FIG. 5 is a block diagram showing a structure of a phased array radar 100 including n (n being an integer larger than 1) transmitting/receiving antennas. In the description hereinafter, the term “phase shifter” means an infinite phase shifter. Here, n transceivers of the phased array radar 100 are referred to as a branch-1, a branch-2, . . . , a branch-n. Taking the branch-n as an example, a local oscillator 10 generates a high-frequency wave cos ωt, and a phase shifter 21-n delays the phase of the high-frequency wave cos ωt by −(n−1)θ to generate a transmission wave TX to be outputted to an amplifier system 31-n. The amplifier system 31-n is a combination of one or more amplifiers and a filter. The output of the amplifier system 31-n is inputted to a circulator 40-n. The circulator 40-n outputs the amplified transmission wave TX to an antenna 50-n. In this way, when high-frequency waves cos ωt, cos(ωt−θ), . . . , cos {ωt−(n−1)θ} are outputted as the transmit waves TX from the antennas 50-1, 50-2, . . . , 50-n of the branch-1, branch-2, . . . , branch-n, a beam is generated in the azimuth of ψ. If the antennas 50-1, 50-2, . . . , 50-n are disposed straight in a row in this order at an interval of d, the azimuth angle of ψ is determined by the equation of d sin ψ=λθ/2Π, when the direction perpendicular to the row is set to 0 degrees, and the wavelength of the high-frequency wave is λ. As explained above, by supplying the antennas 50-1, 50-2, . . . , 50-n with the high-frequency wave such that each adjacent two of the antennas radiates the transmit waves X having a predetermined phase difference therebetween, a beam can be generated in the direction depending on the phase difference.
On the other hand, the received wave (reflected wave) can be assumed to come substantially from the azimuth direction of ψ. The reflected wave received by the branch-n lags in phase by θ from the reflected wave received by the branch-(n−1).
Accordingly, when the reflected wave received by the branch-1 is cos(ωt+φ), the reflected wave received by the branch-2 is represented as cos(ωt+θ+φ), . . . , and the reflected wave received by the branch-n is represented as cos(ωt+(n−1)θ+φ). Hence, the received wave is processed by each branch in the following way. Taking the branch-n as an example, the received wave RX is outputted from the antenna 50-n to an amplifier system 32-n through the circulator 40-n. The amplifier system 32-n is a combination of one or more amplifiers and a filter. The output of the amplifier system 32-n is inputted into a mixer 60-n. The mixer is also inputted with the output of the local oscillator 10 through a phase shifter 22-n. The phase shifter 22-n shifts the phase of the high-frequency wave cos ωt inputted thereto by (n−1)θ to generate a high frequency-wave cos {ωt+(n−1)θ} Accordingly, the output of the mixer 60-n is represented as cos φ. The outputs of the mixer 60-1, mixer 60-2, . . . , mixer 60-n of the branch-1, branch-2, . . . , mixer 60-n are all cos φ). The outputs of the mixer 60-1, mixer 60-2, . . . , mixer 60-n are added up by a combining amplifier 70 to generate a received beam. The output (received beam) of the combining amplifier 70 is subjected to a radar process (a distance measuring process) for each value of the azimuth ψ.
In the phased array radar 100 shown in FIG. 5, it is not  possible that the transmission distances between the local oscillator 10 and each of the phase shifters 21-1, 21-2, . . . , 21-n and 22-1, 22-2, . . . , 22-n are the same as one another. Also, it is difficult to make the differences in the transmission distances equal to integral multiples of the wavelength of the high-frequency wave. Accordingly, in the phased array radar 100, it is not possible that the high-frequency waves inputted into the phase shifters 21-1, 21-2, . . . , 21-n and 22-1, 22-2, . . . , 22-n are in the same phase. This prevents both the transmit bean and the received beam from having high directivities. Although the phase differences can be eliminated by performing calibration before shipment, it is not possible to eliminate phase errors due to secular variation or temperature variation in the high-frequency circuit section of the phased array radar 100.
The phased array radar 100 is required to be precisely set in the phase difference θ between the outputs of the transmitting-side phase shifters of each adjacent two of the branches, and also the phase difference θ between the outputs of the receiving-side phase shifters of each adjacent two of the branches. In the transmitting side, the phase difference θ may be ensured at the outputs of the amplifier systems 31-1, 31-2, . . . , 32-n (the inputs of the circulators 40-1, 40-2, . . . , 40-n) instead at the phase shifters.
To this end, the offset phase (the phase difference) between the adjacent phase shifters may be adjusted by the below described structure. Here, it is assumed that each of the phase shifters is constituted by a 90-degree hybrid coupler and two mixers. FIG. 6 is a block diagram showing, together with adjacent components of the phase array radar 100, a structure of a digital signal processor 900 for determining an offset between adjacent phase shifters. The configuration shown in FIG. 6 is for calculating an offset phase (a phase difference) between the outputs of the phase shifters 21-1 and 21-2. The output of the phase shifter 21-1 is branched into two components by the amplifier system 31-1, one of which is applied to one input terminal of a symmetrical mixer 80-12. Likewise, the output of the phase shifter 21-2 is branched into two components by the amplifier system 31-2, one of which is applied to the other input terminal of the symmetrical mixer 80-12. The digital signal processor 900 detects the output of the symmetrical mixer 80-12 through a low-pass filter 81-12 and an amplifier 82-12 in order to correct the phase of the output of the phase shifter 21-2. This phase correction is performed by a corrective phase shifter 25-2 which is disposed between the output of the phase shifter 21-2 and the input of the amplifier system 31-2, and operates in accordance with a correction command from the digital signal processor 900. The symmetrical mixer 80-12 is constituted by two mixers having the same structure to receive respectively two inputs supplied symmetrically, and configured to take a sum of these two inputs. The reason of using such a symmetrical mixer is that it is difficult to evenly treat two inputs to obtain a product of these two inputs by a conventional multiplier as explained below with reference to FIGS. 7A, 7B and 7C. FIG. 7A is a circuit diagram of a conventional multiplier of the differential input/differential output type using a Gilbert-cell. FIG. 7B is a block diagram schematically showing the structure of this conventional multiplier, in which the multiplier core is designated by M. As seen from FIG. 7A, two differential input terminals C and D of the multiplier core M are not in symmetrical positions with respect to each other. Accordingly, since the two differential input terminals C and D have different input impedances, the output of the multiplier may vary in phase. To remove this drawback, it is known, as shown in FIG. 7C, to duplex the predistortion stage (P and P′) and the multiplier core (M and M′), one input I1 being applied to one input terminal C of the multiplier core M and one input terminal D′ of the multiplier core M′, the other input I2 being applied to the other input terminal D of the multiplier core M and the other input terminal C′ of the multiplier core M′. By taking the sum of the outputs of the multiplier cores M and M′, it is possible to obtain the product of the inputs I1 and I2 which have been treated symmetrically. For more details, refer to Hans-Martin Rein et al., “A Symmetrical Analog Wide-Band Multiplier IC Operating up to 8 Gb/s” IEEE ISSCC 1991, pp. 118-119.
Next, the structure of the digital signal processor 900 is explained with reference to FIG. 6. The output of the amplifier 82-12 is supplied to a calibration circuit 910 through a switch 931. The output of the amplifier 82-12 is also supplied to a phase-correcting voltage generation circuit 920 through a switch 932. The digital signal processor 900 also includes computation circuits 950 each of which supplies a phase command value to a corresponding one of the phase shifters, although only the phase command value supplied to the phase shifter 21-12 is shown in FIG. 6. Each computation circuit 950 calculates a phase command value θ for a corresponding one of the phase shifters (the phase shifter 21-2 in this example) on the basis of the output of a phase control voltage generation circuit 940, and output the values of cos θ and sine to the phase shifter 21-2. The calibration circuit 910 outputs an offset voltage to the amplifier 82-12, so that the output of the amplifier 82-12 is kept at 0 precisely when the input of the amplifier 82-12 is 0. The phase-correcting voltage generation circuit 920 supplies the corrective phase shifter 25-2 with a correction command value for correcting the phase of the output of the phase shifter 21-2 so that the phases of the outputs of the phase shifters 21-1 and 21-2 become coincident with each other when they receive the same phase command value.
The digital signal processor 900 operates in the following way. Here, it is assumed that the input of the amplifier 82-12 is 0. The input of the amplifier 82-12 may be set to 0 by setting the output of the local oscillator 10 to 0, or by setting the two inputs to the symmetrical mixer 80-12 to 0, or by setting the output of the symmetrical mixer 80-12 to 0, or by setting the output of the low-pass filter 81-1 to 0 by use of an appropriate switch. Since the output (analog voltage) of the amplifier 82-12 has to be 0 at this time, the switch 931 is turned on, and then the analog voltage is detected by the calibration circuit 910. Thereafter, the offset voltage outputted from the calibration circuit 910 to the amplifier 82-12 is adjusted so that the output of the amplifier 82-12 becomes 0. The calibration circuit 910 stores the value of the offset voltage in the form of a digital value. After the offset voltage of the amplifier 82-12 is adjusted, the switch 931 is turned off. Accordingly, digital signal processor 900 needs an A/D converter for converting the analog voltage outputted from the amplifier 82-12 into a digital value, and a D/A converter for converting the digital value indicative of the offset voltage for the calibration stored in the calibration circuit 910.
After the offset voltage of the amplifier 82-12 is adjusted, the phase difference between the outputs of the phase shifters 21-1 and 21-12 is corrected by the corrective phase shifter 25-2. When the correction is performed, the phase command value for the phase shifter 21-1 is set to a value indicating 0 degrees as a phase shift amount, and the phase command value for the phase shifter 21-2 is set to a value indicating 90 degrees as a phase shift amount. Accordingly, the high-frequency wave outputted from the local oscillator 10 and not shifted in phase by the phase shifter 21-1 enters the symmetrical mixer 80-12 after being amplified by the amplifier 31-1. On the other hand, the high-frequency wave outputted from the local oscillator 10 and shifted in phase by 90 degrees by the phase shifter 21-2 and subjected to phase correction as necessary at the corrective phase shifter 25-2 enters the symmetrical mixer 80-12 after being amplified by the amplifier 31-2. Hence, since the two inputs of the symmetrical mixer 80-12 are two high-frequency waves having the same frequency and a phase difference of 90 degrees therebetween, the product of these two inputs becomes 0. If the phase difference between the outputs of the phase shifter 21-1 and 21-2 is (90+δ) degrees, a DC analog voltage proportional to sin δ is outputted from the amplifier 82-12. In this case, the switch 932 is turned on to detect this analog voltage by the phase-correcting voltage generation circuit 920. The phase-correcting voltage generation circuit 920 adjusts a phase-correcting value outputted to the corrective phase shifter 25-2 to make the output of the amplifier 82-12 equal to 0. After the phase-correcting value is adjusted, the switch 932 is turned off. Accordingly, the digital signal processor 900 needs an A/D converter for converting the analog voltage outputted from the amplifier 82-12 into a digital value, and a D/A converter for converting the digital value indicative of the phase-correcting value stored in the phase-correcting voltage generation circuit 920.
In the above described way, the phase of the output of the phase shifter 21-2 is precisely corrected with respect to the phase of the output of the phase shifter 21-1. This process is performed for each adjacent two of all the transmitting-side phase shifters, so that the phase of the output of each of the phase shifters 21-2, 21-3, . . . , 21-(n−1) and 21-n is precisely corrected with respect to the phase of the output of the phase shifter 21-1. By performing the similar process as above, the phase of the output of each of the receiving-side phase shifters 22-2, 22-3, . . . , 22-(n−1) and 22-n is precisely corrected with respect to the phase of the output of the phase shifter 22-1.
As explained above, each of the calibration circuit 910 and the phase-correcting voltage generation circuit 920 needs an A/D converter. This makes the circuit structure of the digital signal processor 900 larger. It is possible to configure one A/D converter to operate as both the A/D converter of the calibration circuit 910 and the A/D converter of the phase-correcting voltage generation circuit 920. In this case, the range of the input voltage of the calibration circuit 910 has to be the same as that of the phase-correcting voltage generation circuit 920. However, since each of the phase shifters 21-1 to 21-n and 22-1 to 22-n is an infinite phase shifter, and the phase-correcting value outputted to the corrective phase shifter 25-2 ranges from 0 to 360 degrees, the accuracy of phase correction at the corrective phase shifter 25-2 is likely to degrade in this case. Furthermore, the digital signal processor 900 needs 2 (n−1) corrective phase shifters for both the transmitting side and the receiving side. This also prevents making the digital signal processor 900 compact in circuit structure.